1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having regions of different conductivity type, and more particularly to a semiconductor device having grooves of different depths for improved device isolation.
2. Description of the Prior Art
The increase in densities of integrated circuits has instigated a trend in isolation technology of using trench or groove formation processes for forming physical gaps between active regions in lieu of the more conventional pn junction and local oxidation (LOCOS.TM.) structures. See, e.g., D. N. K. Wang, et al, "Reactive-Ion Etching Eases Restrictions on Materials and Feature Sizes", Electronics, Nov. 3, 1983, pp. 157,159. Groove isolation is particularly useful in CMOS applications as a method of improving latch-up susceptibility. See, e.g., T. Yamaguchi, et al., "High Speed Latch-up Free 0.5-um Channel CMOS Using Self-Aligned TiSi.sub.2 and Deep-Trench Isolation Technologies", Proceedings IEDM 1983, p. 522. Latch-up can be defined as a state of high excess current accompanied by a low-voltage condition, such that a CMOS device can exhibit parasitic bipolar action, in essence creating a conductive low-impedance path between adjacent devices or substrate areas. Within a well of a CMOS device, a vertical parasitic bipolar device may be formed. In addition, parasitic action can occur laterally between devices within adjacent wells or substrate areas of different conductivity type.
The potential for the occurrence of latch-up increases as circuit density increases (i.e. individual devices are positioned closer together). Conventional techniques for isolating active devices suffer from a density penalty which is greatly reduced by the use of grooves for device isolation.
The type of groove necessary to prevent latch-up differs from the type of groove necessary to obtain isolation, specifically with regard to the physical dimensions of the grooves. In particular, a deeper groove is necessary to prevent latch-up between devices in adjacent regions of different conductivity type (sometimes termed wells), while a shallower groove is sufficient to provide isolation between adjacent devices within the same well. Thus, it is desirable to employ grooves of various types on the same integrated circuit, to provide isolation of devices within and between regions of different conductivity type.